Chip Design & Fabrication Layer
The silicon foundation — from architecture to wafer fabrication
Chip Design & Fabrication Layer
The semiconductor layer is the bedrock of the AI factory. Every FLOP of AI compute originates here — in the transistor-level decisions made by architects and the atomic-scale precision of fabrication.
The Value Chain
graph LR
A[Architecture & RTL] --> B[EDA & Verification]
B --> C[Mask Making]
C --> D[Wafer Fabrication]
D --> E[Advanced Packaging]
E --> F[Test & Assembly]
1. Chip Architecture & Design
Key Players: NVIDIA, AMD, Google, Amazon, Microsoft, Cerebras, Groq, Graphcore, Tenstorrent
| Company | Architecture | Process Node | Key Products |
|---|---|---|---|
| NVIDIA | Blackwell, Hopper, Ampere | TSMC 4N/3N | B200, H100, GB200 NVL72 |
| AMD | CDNA, RDNA | TSMC 5nm/3nm | MI300X, MI325X, MI350 |
| TPU v5/v6 | TSMC 5nm/3nm | Trillium, v5p, v6 | |
| Amazon | Trainium/Inferentia | TSMC 7nm/5nm | Trainium2, Inferentia2 |
| Microsoft | Maia | TSMC 5nm | Maia 100, Cobalt 100 |
| Cerebras | Wafer-Scale Engine | TSMC 7nm/5nm | WSE-3, CS-3 |
| Groq | LPU | TSMC 14nm/4nm | GroqChip, GroqRack |
2. EDA Tools & IP (The “Compiler” for Silicon)
Key Players: Synopsys, Cadence, Siemens EDA, Arm, Imagination Technologies
- Synopsys: DesignWare IP, Fusion Compiler, PrimeTime, VCS simulation
- Cadence: Genus, Innovus, JasperGold, Palladium emulation
- Siemens EDA: Calibre, Questa, Tessent, Catapult HLS
- Arm: Neoverse V2/V3, Cortex-X, Total Compute solutions
3. Wafer Fabrication (Foundries)
Key Players: TSMC, Samsung Foundry, Intel Foundry, GlobalFoundries
| Foundry | Leading Node | Capacity (wafers/mo) | AI Revenue Share |
|---|---|---|---|
| TSMC | N3/N3E/N3P/N2 | ~1.4M (300mm equiv) | ~60%+ |
| Samsung | SF3/SF2 | ~500K | ~15% |
| Intel | 18A/14A | ~300K (ramping) | ~5% |
| GlobalFoundries | 12nm/22nm FDX | ~800K | Specialty |
Critical Bottleneck: ASML EUV Lithography
- High-NA EUV (EXE:5000): $380M per tool, 1-2 year lead time
- Global installed base: ~180 EUV tools (mostly Low-NA)
- TSMC consumes ~70% of global EUV capacity
4. Advanced Packaging (The New Moore’s Law)
Key Players: TSMC, Amkor, ASE, Intel, Samsung
| Technology | Provider | Application | Status |
|---|---|---|---|
| CoWoS-S | TSMC | H100, H200, B100 | Volume production |
| CoWoS-L | TSMC | B200, MI300X, Blackwell | Ramping (bottleneck) |
| CoWoS-R | TSMC | Future HBM4 | Development |
| SoIC | TSMC | 3D stacking, cache on compute | Limited volume |
| EMIB/Foveros | Intel | Ponte Vecchio, Falcon Shores | Ramping |
| I-Cube/H-Cube | Samsung | HBM integration | Volume |
CoWoS Capacity Crisis (2024-2025):
- TSMC CoWoS capacity: ~35K wafers/month (2024) → ~60K (2025 target)
- NVIDIA alone needs ~60% of CoWoS-L for Blackwell
- 18-24 month order backlogs
5. High-Bandwidth Memory (HBM)
Key Players: SK Hynix, Samsung, Micron
| Generation | Bandwidth | Capacity | Stack Height | Key Customers |
|---|---|---|---|---|
| HBM3 | 819 GB/s | 24GB | 8-hi | H100, MI300 |
| HBM3E | 1.2 TB/s | 24-36GB | 8-12-hi | B200, MI325X, GB200 |
| HBM4 | 1.5+ TB/s | 48GB+ | 12-16-hi | 2025/2026 (Rubin, MI400) |
Market Share (2024):
- SK Hynix: ~50% (HBM3E leader)
- Samsung: ~40% (catching up on HBM3E 12-hi)
- Micron: ~10% (ramping HBM3E)
Investment Requirements (Per AI Factory)
| Component | CapEx per 100K GPU Cluster | Lead Time |
|---|---|---|
| Wafer allocation (TSMC N3) | $2-3B | 12-18 months |
| CoWoS-L packaging | $500M-1B | 18-24 months |
| HBM3E 12-hi supply | $1-2B | 12-18 months |
| Test & assembly | $200-500M | 6-12 months |
The chip layer determines the maximum theoretical performance of the entire AI factory. Every downstream layer — servers, racks, datacenters, power — exists to feed and cool these silicon engines.